Archive for December 9th, 2010

3D gets to storage. And it saves energy too!

Thursday, December 9th, 2010 by Roberto Saracco

Samsung has announced the availability of a new generation of memory chip produced at 40nm scale using a 3D connection among its transistors. Unlike current generation of memory chip where connection among the transistors takes place on a horizontal layer this new generation of chips can also connect vertically thus allowing the layering of transistor, stacking them up. This leads to denser memory, higher capacity and less energy consumed. This technology, known under the name of TSV, Through Silicon Via,  will also be used on the following generation at 30nm scale.

New generations of memory chips provide more capacity and consume less energy

New generations of memory chips provide more capacity and consume less energy

http://www.samsung.com/global/business/semiconductor/Greenmemory/Applications/ServerStorage/ServerStorage_DDR3.html

The chip announced by Samsung has a 8GB capacity (a 50% increase in capacity) and requires 40% less energy. Its first applications will be in the server market but as it always happened in a few year will move to the mass market eventually ending up in our cell phones.

Indeed, there is no limit in sight to the ever growing storage capacity. Along with the increase in processing and transmission, as I noted few days ago, this will lead to significantly different infrastructure architectures by the end of this decade.